The present invention relates in general to semiconductor manufacturing. More particularly, it relates to a semiconductor device with improved sidewall spacers and a method for fabricating the same.
Silicides are commonly used to reduce the gate resistance and the source/drain resistance between adjacent gate electrodes. As the physical geometry of semiconductor devices shrinks, however, the spacing between gate electrodes shrinks as well. The available space for silicide formation shrinks faster than the ground rules for gate-to-gate spacing due to the finite width of the gate spacers. Thus, the formation of silicide in narrow spaces between gates becomes more difficult, leading to an elevated and variable resistance in these regions. Furthermore, dry etching of conventional sidewall spacers is difficult to control and can result in variations in spacer width between adjacent gates. These variations in spacer width further result in poor resistance uniformity.
Referring now to FIG. 1, a cross-section of a partially completed semiconductor device is shown. Two transistor gate patterns 12 are formed overlying the semiconductor substrate 10. The gate patterns 12 include a gate electrode 14 overlying a gate dielectric 16. An oxide liner layer 18 and a silicon nitride layer 20 are deposited in sequence overlying the gate patterns 12 and the semiconductor substrate 10. Note that the silicon nitride layer 20 is much thicker than the oxide liner layer 18. For example, for 80 nm node design rule, the thicknesses of the silicon nitride layer 20 and the oxide liner layer 18 are about 650 Å and 130 Å, respectively.
Referring to FIGS. 2 and 3, conventional spacer etching is performed to provide an L-shaped oxide spacer 18a and a thicker nitride spacer 20a. After formation of source/drain regions 22, silicides 24 are formed on the exposed surface of the gate electrode 14 and the source/drain regions 22. As the available spaced for silicide formation is determined by the spacer widths, the variations in spacer width will result in poor resistance uniformity. With the conventional spacer scheme of FIG. 2, however, large variations in spacer width during spacer etching often necessitates complex process tuning. A novel spacer scheme with better width control is desirable. It is also desirable to reduce the spacer width to enlarge the space for silicide formation.
Another problem associated with conventional spacers is limited top loss. Referring back to FIG. 2, only a trivial sidewall portion of the gate electrode 14 is exposed after the spacer dry etching. With the finite exposed area, silicide is difficult to form to provide a high-performance transistor. It would be advantageous for the gate electrode to have a larger area for silicidation.
FIG. 4 shows yet another problem with conventional spacers. A contact hole 30 is etched though an inter-level dielectric (ILD) layer 28 and a contact etch stop layer 26 to expose the source/drain regions 22. As the stop layer 26 is typically silicon nitride, the nitride spacer 20a is laterally etched during the contact etching process for removal of the stop layer 26, leading to undercut 30a. The lateral etch poses reliability risks especially when the contact hole 30 is misaligned.